In recent years, a so-called Fin type FET has been proposed as a type of MIS type field effect transistor (hereinafter referred to as “FET”). This Fin type FET has a rectangular parallelepiped protrusive semiconductor layer protruding in a vertical direction to the plane of a substrate, and a gate electrode is provided so as to straddle the protrusive semiconductor layer from one side surface thereof to the opposite side surface across the upper surface. A gate electrode is interposed between the protrusive semiconductor layer and the gate electrode, and channels are formed mainly along the opposite side surfaces of the protrusive semiconductor layer. Such a Fin type FET is known to be advantageous for miniaturization because the channel width can be situated in a direction vertical to a substrate plane, and also advantageous for improvements of various kinds of characteristics such as improvements of the cut-off characteristic and carrier mobility and reduction of the short channel effect and punch-through.
As such a Fin type FET, Patent Document 1 (Japanese Patent Laid-Open No. 64-8670) discloses a MOS field effect transistor characterized in that a semiconductor portion having a source region, a drain region and a channel region is a rectangular parallelepiped having side surfaces almost vertical to the flat surface of a wafer substrate, the height of the rectangular parallelepiped semiconductor portion is greater than the width thereof, and a gate electrode extends along a direction vertical to the flat surface of the wafer substrate.
Patent Document 1 shows as an example a configuration in which a part of the rectangular parallelepiped semiconductor portion is a part of a silicon wafer substrate and a configuration in which a part of the rectangular parallelepiped semiconductor portion is a part of a monocrystalline silicon layer of an SOI (Silicon On Insulator). The former is shown in FIG. 1(a) and the latter is shown in FIG. 1(b).
In the configuration shown in FIG. 1(a), a part of a silicon wafer substrate 101 is a rectangular parallelepiped portion 103, and a gate electrode 105 extends to one side to the opposite side across the top of the rectangular parallelepiped portion 103. In the rectangular parallelepiped portion 103, a source region and a drain region are formed in portions on opposite sides of the gate electrode, and a channel is formed in a portion below an insulating film 104 below the gate electrode. The channel width is equivalent to double the height (h) of the rectangular parallelepiped portion 103, and the gate length corresponds to the width L of the gate electrode 105. The rectangular parallelepiped portion 103 is formed of a portion left inside of a trench formed by anisotropically etching the silicon wafer substrate 101. Furthermore, the gate electrode 105 is provided so as to straddle the rectangular parallelepiped portion 103 on an insulating film 102 formed in the trench.
In the configuration shown in FIG. 1(b), an SOI substrate consisting of a silicon wafer substrate 111, an insulating layer 112 and a silicon monocrystalline layer is prepared, the silicon monocrystalline layer is patterned to form a rectangular parallelepiped portion 113, and a gate electrode 115 is provided on the exposed insulating layer 112 so as to straddle the rectangular parallelepiped portion 113. In the rectangular parallelepiped portion 113, a source region and a drain region are formed in portions on opposite sides of the gate electrode, and a channel is formed in a portion below an insulating film 114 below the gate electrode. The channel width is equivalent to the sum of double the height (a) of rectangular parallelepiped portion 113 and the width (b) thereof, and the gate length corresponds to the width L of the gate electrode 115.
Patent Document 2 (Japanese Patent Laid-Open No. 2002-118255) discloses a Fin type FET having a plurality of rectangular parallelepiped semiconductor portions (raised semiconductor layers 213) shown in, for example, FIGS. 2(a) to 2(c). FIG. 2(b) is a sectional view taken along line B-B of FIG. 2(a), and FIG. 2(c) is a sectional view taken along line C-C of FIG. 2(a). The Fin type FET has a plurality of raised semiconductor layers 213 formed of a part of a well layer 211 of a silicon substrate 210, these layers are arranged in parallel, and a gate electrode 216 is provided so as to straddle the central portions of these raised semiconductor layers. The gate electrode 216 is formed along the side surface of each raised semiconductor layer 213 from the upper surface of an insulating film 214. An insulating film 218 is interposed between each raised semiconductor layer and the gate electrode, and a channel 215 is formed on the raised semiconductor layer below the gate electrode. A source/drain region 217 is formed on each raised semiconductor layer, and a high-concentration impurity layer (punch-through stopper layer) is provided in a region 212 below the source/drain region 217. Upper wirings 229 and 230 are provided on an interlayer insulating film 226, and each upper wiring is connected to the source/drain region 207 and the gate electrode 216 by each contact plug 228. It is described that according to such a structure, the side surface of the raised semiconductor layer may be used as a channel width, and therefore a planar area can be decreased as compared to a conventional FET of planar type.